1. Field of the Invention
The subject invention relates generally to the field of semiconductor device fabrication and, more specifically, to the fabrication of an integral capacitor structure in a semiconductor device.
2. Description of the Art
The fabrication of a semiconductor wafer to create a semiconductor integrated circuit device typically involves a sequence of processing steps that fabricate the multi-layer structure of integrated circuits comprising integrated circuit components generally associated with the integrated circuit device. Such processing steps may include (1) the deposition of metals, dielectrics, and semiconductor films on the semiconductor wafer, (2) the creation of masks by lithography techniques, (3) the doping of semiconductor layers by diffusion or implantation, (4) the polishing of various layers (e.g. chemical-mechanical polishing), and (5) the etching of various layers for selective or blanket material removal.
Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are applied on or in a surface of a wafer, or on or in a surface of a previous layer. These layers can constitute a metal pattern forming various elements of an electrical circuit. Insulating material and dielectric material are added at various stages of the fabrication process. The layers are typically treated to create a smooth, planar surface.
In forming a semiconductor device, one common practice has been to use deposition techniques to apply a particular layer to an existing substrate or layer. In one type of process, such as vapor deposition, reactant gas(s) in a carrier gas, are provided through a tube wherein the gas(s) reacts with the wafer. In a typical vapor deposition process, the thickness of the thin film layer is measured following completion of the deposition. Under these circumstances, the film thickness is generally controlled by the amount of time that the device is exposed to the vapor deposition process. The subsequent measurement of the film thickness is often accomplished in a “go/no-go” manner in which devices having a film thickness falling outside a predetermined thickness range are rejected and scrapped. In other cases, the semiconductor device is returned for further processing, either for additional material deposition, or for material removal such as in a polishing process. Ordinarily, the economics of mass production mitigate in favor of simply scrapping the component.
During the fabrication process, a portion or portions of a layer may be removed. This may be accomplished by chemical mechanical polishing (CMP). CMP is used to selectively remove a portion or portions of a layer of the semiconductor device and/or remove a portion or portions of substrate of the semiconductor device. Typically, a CMP planarization of a wafer involves holding the wafer against a rotating polishing pad that is subjected to a slurry such as a silica-based alkaline slurry. The polishing pad also applies pressure against the wafer.
While it is desirable to use CMP planarization during the fabrication of semiconductor devices, the CMP planarization step may present some problems and drawbacks. For example, each additional CMP step leads to additional costs and additional processing time in the semiconductor fabrication process.
Additionally, a CMP step on a newly formed layer on the wafer may cause alignment targets thereon to lose their steps after the CMP method is performed. The CMP planarization step may also lead to “over polishing” (i.e. removal of material that was not intended to be removed). All of the above results may contribute to defective devices, loss of device yield, and lack of device reliability.
In view of the above, it is desirable to form constituent parts and/or components of a semi-conductor device with as little additional steps as possible. Such constituent parts and/or components include transistors, capacitors, and the like.
What is therefore needed in view of the above, is a system, method and/or apparatus for fabricating multiple components of a semi-conductor device during a common step of the fabrication process.
What is therefore further needed in view of the above is a system, method and/or apparatus for fabricating a capacitor of a semi-conductor device at the same time as fabrication of at least a portion of a transistor of the semi-conductor device.